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Dynamic address sizing is made possible because of a six bit address modifier code [AM0-AM5] which accompanies each address. This can be thought of as a tag that is attached to each address. There are 47 defined address modifier codes, which are summarized in the table below.
|0x3F||24||A24 supervisory block transfer (BLT)|
|0x3E||24||A24 supervisory program access|
|0x3D||24||A24 supervisory data access|
|0x3C||24||A24 supervisory 64-bit block transfer (MBLT)|
|0x3B||24||A24 non-privileged block transfer (BLT)|
|0x3A||24||A24 non-privileged program access|
|0x39||24||A24 non-privileged data access|
|0x38||24||A24 non-privileged 64-bit block transfer (MBLT)|
|0x37||40||A40BLT [MD32 data transfer only]|
|0x36||-||Unused / reserved|
|0x35||40||A40 lock command (LCK)|
|0x33||-||Unused / reserved|
|0x32||24||A24 lock command (LCK)|
|0x30 - 0x31||-||Unused / reserved|
|0x2F||24||CR / CSR space|
|0x2E||-||Unused / reserved|
|0x2D||16||A16 supervisory access|
|0x2C||16||A16 lock command (LCK)|
|0x2A - 0x2B||-||Unused / reserved|
|0x29||16||A16 non-privileged access|
|0x22 - 0x28||-||Unused / reserved|
|0x21||32 or 40||2eVME for 3U bus modules (address size in XAM code)|
|0x20||32 or 64||2eVME for 6U bus modules (address size in XAM code)|
|0x10 - 0x1F||-||User defined|
|0x0F||32||A32 supervisory block transfer (BLT)|
|0x0E||32||A32 supervisory program access|
|0x0D||32||A32 supervisory data access|
|0x0C||32||A32 supervisory 64-bit block transfer (MBLT)|
|0x0B||32||A32 non-privileged block transfer (BLT)|
|0x0A||32||A32 non-privileged program access|
|0x09||32||A32 non-privileged data access|
|0x08||32||A32 non-privileged 64-bit block transfer (MBLT)|
|0x06 - 0x07||-||Unused / reserved|
|0x05||32||A32 lock command (LCK)|
|0x04||64||A64 lock command (LCK)|
|0x03||64||A64 block transfer (BLT)|
|0x02||-||Unused / reserved|
|0x01||64||A64 single access transfer|
|0x00||64||A64 64-bit block transfer (MBLT)|
During a bus cycle the VMEbus master tags each address with an address modifier code. Slaves monitor these codes so they can determine which address lines to monitor. A16 addresses are decoded from A01-A15, A24 addresses from A01-A23 and so on.
The address modifier code also indicates the type of bus transaction. It discriminates between instruction fetches, data cycles and so on. Originally, this information was intended for debugging purposes. In the early days of VMEbus it was fairly common to fetch microprocessor instructions across the backplane. This allowed logic analyzers to separate them from data cycles, and was a very powerful debugging tool.
Today, instructions are rarely fetched across VMEbus because they are generally stored in local (CPU) memory. Local memories are now fast, large and cheap, and VMEbus creates a significant bottleneck. Most people use VMEbus as an I/O channel for passing data between CPU cards and peripherals.
Some of the information in the address modifier codes is obsolete. For example, the A24 codes contain supervisory and non-privileged modes. These corresponded directly to the 68000 microprocessor supervisor and user modes, and were an early attempt at memory management. However, this function is now performed on (local) memory management IC's (MMU's), thereby rendering this data useless.
The address modifier codes are ignored during interrupt acknowledge cycles. IACK* is a signal asserted by interrupt handlers to show that the current cycle is an interrupt acknowledge cycle, and negated by masters to show that it is a data transfer cycle. It is sometimes useful to think of IACK* as a seventh address modifier bit.
Address modifier codes also simplify the design (and lower the cost) of many VMEbus modules. Modules can be as simple or as complex as the application requires. Slaves, like serial I/O modules, require only several bytes of address space and can use A16 addressing. This reduces the number of parts on a board by decreasing the number of comparator and control logic ICs. This lowers the board cost and conserves space. More complex modules, such as memory or graphic controllers, must use A24 or A32 addressing because of their large memory spaces.
The address modifiers also make single (3U) and double height (6U) modules compatible. Single height modules use only the P1/J1 connector, and can only monitor address lines A01-A23. This limits these modules to the A16, A24 and A40 cycles. Double height modules can monitor an additional eight address lines on the P2/J2 connector, so they can also perform 32 and 64-bit address transfers. Without the address modifier code, the simple P2/J2 expansion bus would have been awkward.
The 2eVME (two-edge) VMEbus cycles also contain an extended address modifier code (XAM). This code was added because many of the address modifier codes have been used up, and allows more codes to be defined for future bus cycles.
This page last updated: Jul 28, 2000
Copyright 1999 Wade D. Peterson. All rights reserved.